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ltc3822-1 1 38221f typical application features applications description no r sense tm , low input voltage, synchronous step-down dc/dc controller the ltc ? 3822-1 is a synchronous step-down switching regulator controller that drives external n-channel power mosfets using few external components. the constant frequency current mode architecture with mosfet v ds sensing eliminates the need for sense resistors and im- proves ef? ciency. burst mode operation provides high ef? ciency at light loads. the 99% maximum duty cycle provides low dropout operation, extending operating time in battery-powered systems. the operating frequency can be programmed up to 750khz, allowing the use of small surface mount inductors and ca- pacitors. for noise sensitive applications, the ltc3822-1 can be synchronized to an external clock from 250khz to 750khz. the ltc3822-1 is available in the tiny footprint thermally enhanced 12-pin dfn package or 16-pin narrow ssop package. dual n-channel mosfet synchronous drive no current sense resistor required optimized for 3.3v in and li-ion applications constant frequency current mode operation for excellent line and load transient response 1% 0.6v reference low dropout operation: 99% duty cycle phase-lockable or adjustable frequency: 250khz to 750khz internal soft-start circuitry tracking and adjustable soft-start input selectable maximum peak current sense threshold selectable burst mode ? / forced continuous/pulse skipping mode at light load digital run control pin output overvoltage protection micropower shutdown: i q = 7.5a tiny thermally enhanced 12-pin (3mm 3mm) dfn or 16-pin narrow ssop packages single cell li-ion powered systems 3.3v in systems v in iprg ltc3822-1 run plllpf v fb tg sw 0.1 f 1nf 10.2k 59k 118k 38221 ta01 0.47 h 47 f 2 boost track/ss sync/mode bg i th gnd gnd 47 f 2 v out 1.8v 8a v in 3.3v , lt, ltc, ltm and burst mode are registered trademarks of linear technology corporation. no r sense is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by patents, including 5481178, 5929620, 6580258, 6304066, 5847554, 6611131, 6498466, 5705919. ltc3822-1 ltc3822 light load operation continuous, discontinuous or burst mode operation discontinuous mode package dd12 (3mm 3mm), gn16 dd10 (3mm 3mm), ms10e tracking/soft-start yes internal soft-start only external sync yes no pgood pin gn16 only no ef? ciency/power loss vs load current load current (ma) 10 40 efficiency (%) power loss (w) 50 60 70 80 100 1000 10000 38221 ta01b 30 20 10 0 90 100 burst mode efficiency burst mode power loss 1 0.1 0.01 0.001 10 v in = 3.3v v out = 1.8v figure 10 circuit
ltc3822-1 2 38221f package/order information electrical characteristics absolute maximum ratings input supply voltage (v in ) ........................ C0.3v to 4.5v boost voltage .......................................... C0.3v to 10v plllpf, run, iprg, sync/mode, track/ss voltages .......................C0.3v to (v in + 0.3v) v fb , i th voltages ....................................... C0.3v to 2.4v sw voltage ............................................ C2v to v in + 1v operating temperature range (note 2) ... C40c to 85c (note 1) top view 13 dd package 12-lead (3mm 3mm) plastic dfn 12 11 8 9 10 4 5 3 2 1 sw v in boost tg bg iprg plllpf sync/mode track/ss v fb i th run 6 7 t jmax = 125c, ja = 43c/w exposed pad (pin 13) is gnd, must be soldered to pcb gn package 16-lead plastic ssop 1 2 3 4 5 6 7 8 top view 16 15 14 13 12 11 10 9 gnd plllpf sync/mode pgood track/ss v fb i th run sw sense C v in boost tg bg iprg gnd t jmax = 125c, ja = 110c/w order part number dd part marking order part number gn part marking ltc3822edd-1 lcms ltc3822egn-1 38221 order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/ consult ltc marketing for parts speci? ed with wider operating temperature ranges. the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 3.3v unless otherwise noted. storage ambient temperature range dd ..................................................... C65c to 125c gn ..................................................... C65c to 150c junction temperature (note 3) ............................. 125c lead temperature (soldering, 10 sec) gn only ............................................................ 300c parameter conditions min typ max units main control loops v in operating voltage range 2.75 3.3 4.5 v input dc supply current normal operation sleep mode shutdown uvlo (note 4) run = 0 v in = uvlo threshold C 200mv 360 105 7.5 10 525 150 20 20 a a a undervoltage lockout threshold v in falling v in rising 1.95 2.15 2.25 2.45 2.55 2.75 v v shutdown threshold of run pin 0.7 1.1 1.4 v regulated feedback voltage (note 5) 0.594 0.6 0.606 v output voltage line regulation 2.75v < v in < 4.5v (note 5) 0.025 0.1 %/v
ltc3822-1 3 38221f note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3822e-1 is guaranteed to meet speci? ed performance from 0c to 85c. speci? cations over the C40c to 85c operating range are assured by design characterization, and correlation with statistical process controls. parameter conditions min typ max units output voltage load regulation i th = 1.3v to 0.9v (note 5) i th = 1.3v to 1.7v 0.1 C0.1 0.5 C0.5 % % track/ss pull-up current track/ss = 0v 0.65 1 1.35 a v fb input current (note 5) 10 50 na overvoltage protect threshold measured at v fb 0.66 0.68 0.70 v overvoltage protect hysteresis 20 mv top gate (tg) drive rise time c l = 3000pf 40 ns top gate (tg) drive fall time c l = 3000pf 40 ns bottom gate (bg) drive rise time c l = 3000pf 50 ns bottom gate (bg) drive fall time c l = 3000pf 40 ns maximum duty cycle in dropout 99 % maximum current sense voltage (v in C sw) ( v sense(max) ) iprg = floating iprg = 0v iprg = v in 110 70 185 125 82 200 140 95 220 mv mv mv soft-start time time for v fb to ramp from 0.05v to 0.55v 650 s oscillator oscillator frequency plllpf = floating plllpf = 0v plllpf = v in 480 240 640 550 300 750 600 340 850 khz khz khz phase-locked loop lock range sync/mode clocked minimum synchronizable frequency maximum synchronizable frequency 750 200 1000 250 khz khz phase detector output current sinking sourcing f osc > f sync/mode f osc < f sync/mode C5 5 a a pgood output (gn package only) pgood voltage low i pgood sinking 1ma 100 mv pgood trip level v fb with respect to set output voltage v fb < 0.6v, ramping postive v fb < 0.6v, ramping negative v fb > 0.6v, ramping negative v fb > 0.6v, ramping positive C13 C16 7 10 C10.0 C13.3 10.0 13.3 C7 C10 13 16 % % % % electrical characteristics the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 3.3v unless otherwise noted. note 3: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: t j = t a + (p d ? ja ) note 4: dynamic supply current is higher due to gate charge being delivered at the switching frequency. note 5: the ltc3822-1 is tested in a feedback loop that servos i th to a speci? ed voltage and measures the resultant v fb voltage.
ltc3822-1 4 38221f typical performance characteristics ef? ciency/power loss vs load current load step (continuous mode) regulated feedback voltage vs temperature undervoltage lockout threshold vs temperature shutdown (run) threshold vs temperature maximum current sense threshold vs temperature oscillator frequency vs temperature t a = 25c unless otherwise noted. temperature ( c) C50 0.596 feedback voltage (v) 0.597 0.598 0.600 0.599 0.601 0.602 100 38212 g06 0.603 0.604 050 temperature ( c) C60 2.15 2.20 2.25 input voltage (v) 2.30 2.35 2.40 2.45 C20 20 60 100 38221 g07 2.50 2.55 C40 0 40 80 v in rising v in falling temperature ( c) C60 1.00 run voltage (v) 1.05 C20 20 60 100 38221 g08 1.15 1.10 1.20 C40 0 40 80 temperature ( c) C60 115 120 maximum current sense threshold (mv) 125 130 135 C20 20 60 100 3822 g09 C40 0 40 80 iprg = float temperature ( c) C60 C10 C8 C6 normalized frequency shift (%) C4 C2 0 4 C20 20 60 100 38221 g10 8 2 6 10 C40 0 40 80 load current (ma) 10 40 efficiency (%) power loss (w) 50 60 70 80 100 1000 10000 38221 g01 30 20 10 0 90 100 1 10 0.1 0.01 0.001 100 figure 10 circuit burst mode operation pulse skipping continuous mode efficiency power loss v in = 3.3v, v out = 1.8v load step (pulse skip mode) v out ac coupled 200mv/div inductor current 2a/div figure 10 circuit 50 s/div 38221 g02 v out ac coupled 200mv/div inductor current 2a/div figure 10 circuit 50 s/div 38221 g04 load step (burst mode operation) v out ac coupled 200mv/div inductor current 2a/div figure 10 circuit 50 s/div 38221 g05
ltc3822-1 5 38221f maximum current sense voltage vs i th pin voltage oscillator frequency vs input voltage shutdown quiescent current vs input voltage quiescent current in normal operation vs input voltage i th voltage (v) 0.5 C20 current limit (%) 0 20 40 60 100 1 1.5 38221 g03 2 80 burst mode operation (i th rising) burst mode operation (i th falling) forced continuous mode pulse skipping mode typical performance characteristics t a = 25c unless otherwise noted. input voltage (v) 2.5 C5 C4 C3 normalized frequency shift (%) C2 C1 0 2 4.0 38221 g11 4 1 3 5 3.0 3.5 4.5 input voltage (v) 2.5 0 2 shutdown current ( a) 4 6 8 12 4.5 38221 g12 16 10 14 18 3.5 3.0 4.0 input voltage (v) 2.5 quiescent current ( a) 360 4.5 3822 g13 380 370 390 340 330 350 3.5 3.0 4.0 v run 1v/div v out 1v/div figure 10 circuit v in = 3.3v v out = 1.8v r load = 1.5 ? 200 s/div 38221 g14 v run 1v/div v out 1v/div v track/ss 1v/div figure 10 circuit v in = 3.3v v out = 1.8v r load = 1.5 ? c ss = 0.01 f 4ms/div 38221 g15 start-up with internal soft-start start-up with external soft-start capacitor soft-start with tracking continuous mode operation v out 1v/div v track/ss 500mv/div figure 10 circuit v in = 3.3v v out = 1.8v r load = 1.5 ? 4ms/div 38221 g16 v out 20mv/div ac coupled i l 2a/div v sw 2v/div figure 10 circuit v in = 3.3v v out = 1.8v, 100ma 2 s/div 38221 g17
ltc3822-1 6 38221f pin functions plllpf (pin 1/pin 2): this pin serves as the frequency select input and pll lowpass ? lter compensation point. when sync/mode has a dc voltage on it, tying this pin to gnd selects 300khz operation; tying this pin to v in selects 750khz operation. floating this pin selects 550khz operation. when sync/mode has a clock applied to it, connect an r-c network from this pin to ground. sync/mode (pin 2/pin 3): this pin performs two func- tions: 1) external clock synchronization input for phase- locked loop and 2) burst mode, pulse skipping or forced continuous mode select. applying a clock with frequency between 250khz and 750khz causes the internal oscilla- tor to phase-lock to the external clock and disables burst mode operation, but allows pulse skipping at low load currents. to select burst mode operation at light loads, tie this pin to v in . grounding this pin selects forced continuous operation, which allows the inductor current to reverse. tying this pin to a voltage greater than 0.4v and less than 1.2v selects pulse skipping mode. in these cases, the frequency of the internal oscillator is set by the voltage on the plllpf pin. track/ss (pin 3/pin 5): tracking input for the control- ler or optional external soft-start input. this pin allows the start-up of v out to track the external voltage at this pin using an external resistor divider. the ltc3822-1 regulates the v fb voltage to the smaller of 0.6v or the voltage on the track/ss pin. an internal 1a pull-up current source is connected to this pin. tying this pin to v in allows v out start-up with the internal 1ms soft-start clamp. an external soft-start can be programmed by con- necting a capacitor between this pin and ground. do not leave this pin ? oating. v fb (pin 4/pin 6): feedback pin. this pin receives the remotely sensed feedback voltage for the controller from an external resistor divider across the output. i th (pin 5/pin 7): current threshold and error ampli? er compensation point. nominal operating range on this pin is from 0.7v to 2v. the voltage on this pin determines the threshold of the main current comparator. run (pin 6/pin 8): run control input. forcing this pin below 1.1v shuts down the chip. driving this pin to v in or releasing this pin enables the chip to start-up. iprg (pin 7/pin 10): three-state pin to select the maxi- mum peak sense voltage threshold. this pin selects the maximum allowed voltage drop between the v in and sw pins (i.e., the maximum allowed drop across the external topside mosfet). tie to v in , gnd or ? oat to select 200mv, 82mv or 125mv respectively. (dd/gn) typical performance characteristics t a = 25c unless otherwise noted. pulse skip mode operation burst mode operation v out 20mv/div ac coupled i l 2a/div v sw 2v/div figure 10 circuit v in = 3.3v v out = 1.8v, 100ma 2 s/div 38221 g18 v out 20mv/div ac coupled i l 2a/div v sw 2v/div figure 10 circuit v in = 3.3v v out = 1.8v, 100ma 10 s/div 38221 g19
ltc3822-1 7 38221f pin functions (dd/gn) bg (pin 8/pin 11): bottom gate driver output. this pin drives the gate of the external bottom-side mosfet. this pin has an output swing from gnd to boost. tg (pin 9/pin 12): top gate driver output. this pin drives the gate of the external topside mosfet. this pin has an output swing from gnd to boost. boost (pin 10/pin 13): positive supply pin for the gate driver circuitry. a bootstrapped capacitor, charged with an external schottky diode and a boost voltage source, is connected between the boost and sw pins. voltage swing at the boost pin is from boost source voltage (typically v in ) to this boost source voltage + v in . v in (pin 11/pin 14): this pin powers the control circuitry and serves as the positive input to the differential current comparator. sw (pin 12/pin 16): switch node connection to inductor. this pin is also the negative input to the differential current comparator(dfn only) and an input to the reverse current comparator. normally this pin is connected to the source of the external topside mosfet, the drain of the external bottom-side mosfet, and the inductor. exposed pad (pin 13, dd only): ground. the exposed pad is ground and must be soldered to the pcb ground for electrical contact and optimal thermal performance. gnd (pins 1, 9 gn only): ground. pgood (pin 4, gn only): power good output voltage monitor open-drain logic output. this pin is pulled to ground when the voltage on the feedback pin v fb is not within 13.3% of its nominal set point. sense C (pin 15, gn only): negative input to the differential current comparator. normally this pin is connected to the source of the external topside mosfet.
ltc3822-1 8 38221f functional diagram C + C + C + C + C + slope sense + clk icmp r s q boost refresh timeout anti-shoot- through gnd boost tg bg gnd ov sleep burstdis uv 0.68v 0.54v v fb v ref 0.6v trk/ ss i th 38221 fd v fb r c c c sw l m1 m2 c out v out switching logic and blanking circuit r a r b sw fcb gnd C + ricmp i rev t = 1ms internal soft-start run v in v in c in c b v in uvsd v ref 0.6v v in 0.7 a 1 a undervoltage lockout voltage reference sense C track/ss sync/mode plllpf pgood gnd trk/ss burstdis fcb clk ov uv uvsd i prg boost bg clk d b C + + eamp mux v in phase detector v co burst defeat clock detect + 0.15v + 0.3v v in
ltc3822-1 9 38221f operation main control loop the ltc3822-1 uses a constant frequency, current mode architecture. during normal operation, the top external n-channel power mosfet is turned on when the clock sets the rs latch, and is turned off when the current comparator (icmp) resets the latch. the peak inductor current at which icmp resets the rs latch is determined by the voltage on the i th pin, which is driven by the output of the error ampli? er (eamp). the v fb pin receives the output voltage feedback signal from an external resistor divider. this feedback signal is compared to the internal 0.6v reference voltage by the eamp. when the load cur- rent increases, it causes a slight decrease in v fb relative to the 0.6v reference, which in turn causes the i th voltage to increase until the average inductor current matches the new load current. while the top n-channel mosfet is off, the bottom n-channel mosfet is turned on until either the inductor current starts to reverse, as indicated by the current reversal comparator ricmp, or the beginning of the next cycle. shutdown, soft-start and tracking start-up (run and track/ss pins) the ltc3822-1 is shut down by pulling the run pin low. in shutdown, all controller functions are disabled and the chip draws only 7.5a. the tg and bg outputs are held low (off) in shutdown. releasing the run pin allows an internal 0.7a current source to pull up the run pin to v in . the controller is enabled when the run pin reaches 1.1v. the start-up of v out is based on the three different con- nections on the track/ss pin. the start-up of v out is controlled by the ltc3822-1s internal soft-start when track/ss is connected to v in . during soft-start, the error ampli? er eamp compares the feedback signal v fb to the internal soft-start ramp (instead of the 0.6v reference), which rises linearly from 0v to 0.6v in about 1ms. this allows the output voltage to rise smoothly from 0v to its ? nal value while maintaining control of the inductor current. the 1ms soft-start time can be changed by connecting the optional external soft-start capacitor c ss between the track/ss and gnd pins. when the controller is enabled by releasing the run pin, the track/ss pin is charged up by an internal 1a current source and rises linearly from 0v to above 0.6v. the error ampli? er eamp compares the feedback signal v fb to this ramp instead, and regulates v fb linearly from 0v to 0.6v. when the voltage on the track/ss pin is less than the 0.6v internal reference, the ltc3822-1 regulates the v fb voltage to the track/ss pin instead of the 0.6v reference. therefore v out of the ltc3822-1 can track an external voltage v x during start-up. typically, a resistor divider on v x is connected to the track/ss pin to allow the start-up of v out to track that of v x . for coincident tracking during start-up, the regulated ? nal value of v x should be larger than that of v out , and the resistor divider on v x should have the same ratio as the divider on v out that is connected to v fb . see detailed discussions in the run and soft-start/ tracking functions in the applications information section. light load operation (burst mode operation, continuous conduction or pulse skipping mode) (sync/mode pin) the ltc3822-1 can be programmed for either high ef? - ciency burst mode operation, forced continuous conduc- tion mode or pulse skipping mode at low load currents. to select burst mode operation, tie the sync/mode pin to v in . to select forced continuous operation, tie the sync/ mode pin to a dc voltage below 0.4v (e.g., gnd). tying the sync/mode to a dc voltage above 0.4v and below 1.2v (e.g., v fb ) enables pulse skipping mode. when the ltc3822-1 is in burst mode operation, the peak current in the inductor is set to approximate one-fourth of the maximum sense voltage even though the voltage on the i th pin indicates a lower value. if the average induc- tor current is higher than the load current, the eamp will decrease the voltage on the i th pin. when the i th voltage drops below 0.85v, the internal sleep signal goes high and the external mosfets are turned off. in sleep mode, much of the internal circuitry is turned off, reducing the quiescent current that the ltc3822-1 draws. the load current is supplied by the output capacitor. as the output voltage decreases, the eamp increases the i th voltage. when the i th voltage reaches 0.925v, the sleep (refer to functional diagram)
ltc3822-1 10 38221f signal goes low and the controller resumes normal opera- tion by turning on the top n-channel mosfet on the next cycle of the internal oscillator. when the controller is enabled for burst mode or pulse skipping operation, the inductor current is not allowed to reverse. hence, the controller operates discontinuously. the reverse current comparator ricmp senses the drain- to-source voltage of the bottom n-channel mosfet. this mosfet is turned off just before the inductor current reaches zero, preventing it from going negative. in forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. the peak inductor current is determined by the voltage on the i th pin. the top mosfet is turned on every cycle (constant frequency) regardless of the i th pin voltage. in this mode, the ef? ciency at light loads is lower than in burst mode operation. however, continuous mode has the advantages of lower output ripple and no noise at audio frequencies. when the sync/mode pin is clocked by an external clock source to use the phase-locked loop (see frequency selec- tion and phase-locked loop), or is set to a dc voltage between 0.4v and several hundred mv below v in , the ltc3822-1 operates in pwm pulse skipping mode at light loads. in this mode, the current comparator icmp may remain tripped for several cycles and force the external top mosfet to stay off for the same number of cycles. the inductor current is not allowed to reverse (discontinuous operation). this mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced rf interference as compared to burst mode op- eration. however, it provides low current ef? ciency higher than forced continuous mode, but not nearly as high as burst mode operation. during start-up or an undervoltage condition (v fb 0.54v), the ltc3822-1 operates in pulse skipping mode (no current reversal allowed), regardless of the state of the sync/mode pin. short-circuit protection the ltc3822-1 monitors v fb to detect a short-circuit on v out . when v fb is near ground, switching frequency is reduced to prevent the inductor current from running away. the oscillator frequency will progressively return to normal when v fb rises above ground. this feature is disabled during start-up. output overvoltage protection as further protection, the overvoltage comparator (ovp) guards against transient overshoots, as well as other more serious conditions that may overvoltage the output. when the feedback voltage on the v fb pin has risen 13.33% above the reference voltage of 0.6v, the top mosfet is turned off and the bottom mosfet is turned on until the overvoltage is cleared. frequency selection and phase-locked loop (plllpf and sync/mode pins) the selection of switching frequency is a tradeoff between ef? ciency and component size. low frequency opera- tion increases ef? ciency by reducing mosfet switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. the switching frequency of the ltc3822-1s controllers can be selected using the plllpf pin. if the sync/mode is not being driven by an external clock source, the plllpf can be ? oated, tied to v in or tied to gnd to select 550khz, 750khz or 300khz, respectively. a phase-locked loop (pll) is available on the ltc3822-1 to synchronize the internal oscillator to an external clock source that connects to the sync/mode pin. in this case, a series rc should be connected between the plllpf pin and gnd to serve as the plls loop ? lter. the ltc3822-1 phase detector adjusts the voltage on the plllpf pin to align the turn-on of the top mosfet to the rising edge of the synchronizing signal. the typical capture range of the ltc3822-1s phase-locked loop is from approximately 200khz to 1mhz. boost capacitor refresh timeout in order to maintain suf? cient charge on c b , the converter will brie? y turn off the top mosfet and turn on the bottom mosfet if at any time the bottom mosfet has remained off for 10 cycles. this most commonly occurs in a dropout situation where v in is close to v out . operation (refer to functional diagram)
ltc3822-1 11 38221f undervoltage lockout to prevent operation of the mosfets below safe input voltage levels, an undervoltage lockout is incorporated in the ltc3822-1. when the input supply voltage (v in ) drops below 2.25v, the external mosfets and all internal circuits are turned off except for the undervoltage block, which draws only a few microamperes. peak current sense voltage selection and slope compensation (iprg pin) when the ltc3822-1 controller is operating below 20% duty cycle, the peak current sense voltage (between the v in and sense C /sw pins) allowed across the external top mosfet is determined by: ? va vv sense max ith () ? C. 07 10 where a is a constant determined by the state of the iprg pin. floating the iprg pin selects a = 1; tying iprg to v in selects a = 5/3; tying iprg to gnd selects a = 2/3. the maximum value of v ith is typically about 1.98v, so the maximum sense voltage allowed across the external main mosfet is 125mv, 200mv or 82mv for the three respective states of the iprg pin. however, once the controllers duty cycle exceeds 20%, slope compensation begins and effectively reduces the peak sense voltage by a scale factor (sf) given by the curve in figure 1. the peak inductor current is determined by the peak sense voltage and the on-resistance of the main mosfet: i v r pk sense max ds on = ? () () if a sense resistor is used, v sense(max) is the peak cur- rent sense voltage (between the v in and sense C /sw pins) across the sense resistor. the peak inductor is determined by the peak sense voltage and the resistance of the sense resistor: i v r pk sense max sense = ? () power good (pgood) pin (gn only) a window comparator monitors the feedback voltage and pulls the open-drain pgood output pin low when the feedback voltage is not within 10% of the 0.6v reference voltage. pgood is low when the ltc3822-1 is shut down or in undervoltage lockout. operation (refer to functional diagram) duty cycle (%) 10 sf = i/i max (%) 60 80 110 100 90 38221 f01 40 20 50 70 90 30 10 0 30 50 70 20 0 40 60 80 100 figure 1. maximum peak current vs duty cycle
ltc3822-1 12 38221f applications information the typical ltc3822-1 application circuit is shown on the front page of this data sheet. external component selection for the controller is driven by the load require- ment and begins with the selection of the inductor and the power mosfets. power mosfet selection the ltc3822-1s controller requires external n-chan- nel power mosfets for the topside (main) and bottom (synchronous) switches. the main selection criteria for the power mosfets are the breakdown voltage v br(dss) , threshold voltage v gs(th) , on-resistance r ds(on) , reverse transfer capacitance c rss , turn-off delay t d(off) and the total gate charge q g . the gate drive voltage is usually the input supply voltage. since the ltc3822-1 is designed for operation at low input voltages, a sublogic level mosfet (r ds(on) guaranteed at v gs = 2.5v) is required. the topside mosfets on-resistance is chosen based on the required load current. the maximum average load current i out(max) is equal to the peak inductor current minus half the peak-to-peak ripple current i ripple . the ltc3822-1s current comparator monitors the drain-to- source voltage v ds of the top mosfet, which is sensed between the v in and sw pins. the peak inductor current is limited by the current threshold, set by the voltage on the i th pin, of the current comparator. the voltage on the i th pin is internally clamped, which limits the maximum current sense threshold v sense(max) to approximately 125mv when iprg is ? oating (82mv when iprg is tied low; 200mv when iprg is tied high). the output current that the ltc3822-1 can provide is given by: i v r i out max sense max ds on ripple () () () C = ? 2 where i ripple is the inductor peak-to-peak ripple current (see inductor value calculation). a reasonable starting point is setting ripple current i ripple to be 40% of i out(max) . rearranging the above equation yields: r v i ds on max sense max out max () () () ? = 5 6 ? for duty ycycle<20% however, for operation above 20% duty cycle, slope compensation has to be taken into consideration to select the appropriate value of r ds(on) to provide the required amount of load current: rsf v i ds on max sense max out max () () () ?? = 5 6 ? where sf is a scale factor whose value is obtained from the curve in figure 1. these must be further derated to take into account the signi? cant variation in on-resistance with temperature. the following equation is a good guide for determining the re- quired r ds(on)max at 25c (manufacturers speci? cation), allowing some margin for variations in the ltc3822-1 and external component values: rsf v i ds on max sense max out max () () () ?.? ? ? = 5 6 09 ? ? t the t is a normalizing term accounting for the temperature variation in on-resistance, which is typically about 0.4%/c, as shown in figure 2. junction-to-case temperature t jc is about 10c in most applications. for a maximum ambi- ent temperature of 70c, using 80c 1.3 in the above equation is a reasonable choice. the power dissipated in the mosfets strongly depends on their respective duty cycles and load current. when the ltc3822-1 is operating in continuous mode, the duty cycles for the mosfets are: top mosfet duty cycle = v out v bottom mosfet in C duty cycle vv v in out in =
ltc3822-1 13 38221f applications information the mosfet power dissipations at maximum output current are: p v v irv top out in out max t ds on in =+ ??? ? ? () () 22 2 i icf p vv v i out max rss bot in out in out max () () ?? C ? = 22 ?? () tdson r both mosfets have i 2 r losses and the p top equation includes an additional term for transition losses, which are largest at high input voltages. the bottom mosfet losses are greatest at high input voltage or during a short-circuit when the bottom duty cycle is 100%. the ltc3822-1 utilizes a non-overlapping, anti-shoot- through gate drive control scheme to ensure that the mosfets are not turned on at the same time. to function properly, the control scheme requires that the mosfets used are intended for dc/dc switching applications. many power mosfets are intended to be used as static switches and therefore are slow to turn on or off. reasonable starting criteria for selecting the mosfets are that they must typically have a gate charge (q g ) less than 30nc (at 2.5v gs ) and a turn-off delay (t d(off) ) of less than approximately 140ns. however, due to differences in test and speci? cation methods of various mosfet manufacturers, and in the variations in q g and t d(off) with junction temperature ( c) C50 t normalized on resistance 1.0 1.5 150 38221 f02 0.5 0 0 50 100 2.0 figure 2. r ds(on) vs temperature gate drive (v in ) voltage, the mosfets ultimately should be evaluated in the actual ltc3822-1 application circuit to ensure proper operation. shoot-through between the mosfets can most easily be spotted by monitoring the input supply current. as the input supply voltage increases, if the input supply current increases dramatically, then the likely cause is shoot-through. run and soft-start/tracking functions the ltc3822-1 has a low power shutdown mode which is controlled by the run pin. pulling the run pin below 1.1v puts the ltc3822-1 into a low quiescent current shutdown mode (i q = 7.2a). releasing the run pin, an internal 0.7a (at v in = 3.3v) current source will pull the run pin up to v in , which enables the controller. the run pin can be driven directly from logic as showed in figure 3. 3.3v 38221 f03 ltc3822-1 run ltc3822-1 run figure 3. run pin interfacing once the controller is enabled, the start-up of v out is con- trolled by the state of the track/ss pin. if the track/ss pin is connected to v in , the start-up of v out is controlled by internal soft-start, which slowly ramps the positive reference to the error ampli? er from 0v to 0.6v, allowing v out to rise smoothly from 0v to its ? nal value. the de- fault internal soft-start time is around 1ms. the soft-start time can be changed by placing a capacitor between the track/ss pin and gnd. in this case, the soft-start time will be approximately: tc mv a ss ss = ? 600 1 where 1a is an internal current source which is always on. when the voltage on the track/ss pin is less than the internal 0.6v reference, the ltc3822-1 regulates the v fb voltage to the track/ss pin voltage instead of 0.6v. therefore the start-up of v out can ratiometrically track
ltc3822-1 14 38221f an external voltage v x , according to a ratio set by a resis- tor divider at track/ss pin (figure 4a). the ratiometric relation between v out and v x is (figure 4c): v v r r rr rr out x ta a ab ta tb = + + ? for coincident tracking (v out = v x during start-up), r ta = r a , r tb = r b v x should always be greater than v out when using the tracking function of track/ss pin. the internal current source (1a), which is for external soft-start, will cause a tracking error at v out . for example, if a 59k resistor is chosen for r ta , the r ta current will be about 10a (600mv/59k). in this case, the 1a internal current source will cause about 10% (1a/10a ? 100%) tracking error, which is about 60mv (600mv ? 10%) referred to v fb . this is acceptable for most applications. if a better tracking accuracy is required, the value of r ta should be reduced. table 1 summarizes the different states in which track/ss can be used. table 1. the states of the track/ss pin track/ss pin frequency capacitor c ss external soft-start v in internal soft-start resistor divider v out tracking an external voltage v x phase-locked loop and frequency synchronization the ltc3822-1 has a phase-locked loop (pll) comprised of an internal voltage-controlled oscillator (vco) and a phase detector. this allows the turn-on of the external top mosfet to be locked to the rising edge of an external clock signal applied to the sync/mode pin. the phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. this type of phase detector does not exhibit false lock to harmonics of the external clock. the output of the phase detector is a pair of comple- mentary current sources that charge or discharge the external ? lter network connected to the plllpf pin. the relationship between the voltage on the plllpf pin and operating frequency, when there is a clock signal applied to sync/mode, is shown in figure 5 and speci? ed in the electrical characteristics table. note that the ltc3822-1 can only be synchronized to an external clock whose fre- quency is within range of the ltc3822-1s internal vco, which is nominally 200khz to 1mhz. this is guaranteed, applications information time (4b) coincident tracking v x v out output voltage time 38221 f04b,c (4c) ratiometric tracking v x v ou t output voltage ltc3822-1 v fb v out v x track/ss r b r a 38221 f05a r tb r ta figure 4b and 4c. two different modes of output voltage tracking figure 4a. using the track/ss pin to track v x
ltc3822-1 15 38221f over temperature and process variations, to be between 250khz and 750khz. a simpli? ed block diagram is shown in figure 6. if the external clock frequency is greater than the internal oscillators frequency, f osc , then current is sourced con- tinuously from the phase detector output, pulling up the plllpf pin. when the external clock frequency is less than f osc , current is sunk continuously, pulling down the plllpf pin. if the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. the voltage on the plllpf pin is adjusted until the phase and frequency of the internal and external oscillators are identical. at the stable operating point, the phase detector output is high impedance and the ? lter capacitor c lp holds the voltage. the loop ? lter components, c lp and r lp , smooth out the current pulses from the phase detector and provide a stable input to the voltage-controlled oscillator. these ? lter components determine how fast the loop acquires lock. typically r lp = 10k and c lp is 2200pf to 0.01f. typically, the external clock (on sync/mode pin) input high level is 1.6v, while the input low level is 1.2v. table 2 summarizes the different states in which the plllpf pin can be used. table 2. the states of the plllpf pin plllpf pin sync/mode pin frequency 0v dc voltage 300khz floating dc voltage 550khz v in dc voltage 750khz rc loop filter clock signal phase-locked to external clock using a sense resistor (gn only) a sense resistor r sense can be connected between v in and sense C to sense the output load current. in this case, the drain of the topside n-channel mosfet is connected to sense C pin and the source is connected to the sw pin of the ltc3822-1. therefore the current comparator moni- tors the voltage developed across r sense , not the v ds of the top mosfet. the output current that the ltc3822-1 can provide in this case is given by: i v r i out max sense max sense ripple () () C = ? 2 setting ripple current as 40% of i out(max) and using figure 1 to choose sf, the value of r sense is: rsf v i sense sense max out max = ? 5 6 ?? () () variation in the resistance of a sense resistor is much smaller than the variation in on-resistance of an external mosfet. therefore the load current is well controlled with a sense resistor. however the sense resistor causes i 2 r losses in addition to those of the mosfet. therefore, using a sense resistor lowers the ef? ciency of ltc3822-1, especially at high load current. applications information plllpf pin voltage (v) 0.2 0 frequency (khz) 0.7 1.2 1.7 38221 f05 2.2 200 400 600 800 1000 1200 digital phase/ frequency detector oscillator 2.4v r lp c lp 38221 f06 plllpf external oscillator sync/ mode figure 5. relationship between oscillator frequency and voltage at the plllpf pin when synchronizing to an external clock figure 6. phase-locked loop block diagram
ltc3822-1 16 38221f burst mode operation considerations the choice of r ds(on) and inductor value also determines the load current at which the ltc3822-1 enters burst mode operation. when bursting, the controller clamps the peak inductor current to approximately: i v r burst peak sense max ds on () () () ? = 1 4 ? inductor value calculation given the desired input and output voltages, the inductor value and operating frequency f osc directly determine the inductors peak-to-peak ripple current: i v v vv fl ripple out in in out osc = ? ? ? ? ? ? C ? lower ripple current reduces core losses in the inductor, esr losses in the output capacitors, and output voltage ripple. thus, highest ef? ciency operation is obtained at low frequency with a small ripple current. achieving this, however, requires a large inductor. a reasonable starting point is to choose a ripple current that is about 40% of i out(max) . note that the largest ripple current occurs at the highest input voltage. to guarantee that ripple current does not exceed a speci? ed maximum, the inductor should be chosen according to: l vv fi v v in out osc ripple out in C ? ? inductor core selection once the inductance value is determined, the type of in- ductor must be selected. core loss is independent of core size for a ? xed inductor value, but it is very dependent on inductance selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that inductance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! schottky diode selection (optional) the schottky diode d in figure 10 conducts current dur- ing the dead time between the conduction of the power mosfets. this prevents the body diode of the bottom n-channel mosfet from turning on and storing charge during the dead time, which could cost as much as 1% in ef? ciency. a 1a schottky diode is generally a good size for most applications, since it conducts a relatively small average current. larger diodes result in additional transition losses due to their larger junction capacitance. this diode may be omitted if the ef? ciency loss can be tolerated. c in and c out selection in continuous mode, the source current of the top mosfet is a square wave of duty cycle (v out /v in ). to prevent large voltage transients, a low esr input capacitor sized for the maximum rms current must be used. the maximum rms capacitor current is given by: c quired i i vvv v in rms max out in out in re ? ?C / () 12 this formula has a maximum value at v in = 2v out , where i rms = i out /2. this simple worst-case condition is com- monly used for design because even signi? cant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on 2000 hours of life. this makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. several capacitors may be paralleled to meet the size or height requirements in the design. due to the high operating frequency of the ltc3822-1, ceramic capacitors can also be used for c in . always consult the manufacturer if there is any question. applications information
ltc3822-1 17 38221f the selection of c out is driven by the effective series resistance (esr). typically, once the esr requirement is satis? ed, the capacitance is adequate for ? ltering. the output ripple ( v out ) is approximated by: v i esr fc out ripple out + ? ? ? ? ? ? ? ?? 1 8 where f is the operating frequency, c out is the output capacitance and i ripple is the ripple current in the induc- tor. the output ripple is highest at maximum input voltage since i ripple increase with input voltage. topside mosfet drive supply (c b , d b ) in the functional diagram, external bootstrap capaci- tor c b is charged from a boost power source (usually v in ) through diode d b when the sw node is low. when a mosfet is to be turned on, the c b voltage is applied across the gate source of the desired device. when the topside mosfet is on, the boost pin voltage is above the input supply. v boost = 2v in . c b must be 100 times the total input capacitance of the topside mosfet. the reverse breakdown of d b must be greater than v in(max) . note that in applications where the supply voltage to c b exceeds v in , the boost pin will draw approximately 500a in shutdown mode. setting output voltage the ltc3822-1 output voltage is set by an external feed- back resistor divider carefully placed across the output, as shown in figure 7. the regulated output voltage is determined by: vv r r out b a =+ ? ? ? ? ? ? 06 1 .? for most applications, a 59k resistor is suggested for r a . in applications where minimizing the quiescent current is critical, r a should be made bigger to limit the feedback divider current. if r b then results in very high impedance, it may be bene? cial to bypass r b with a 10pf to 100pf capacitor c ff . low input supply voltage although the ltc3822-1 can function down to below 2.4v, the maximum allowable output current is reduced as v in decreases below 3v. figure 8 shows the amount of change as the supply is reduced down to 2.4v. also shown is the effect on v ref . applications information figure 8. line regulation of v ref and maximum sense voltage ltc3822-1 v fb v out r b c ff r a 38221 f07 figure 7. setting the output voltage input voltage (v) 75 normalized voltage or current (%) 85 95 105 80 90 100 2.2 2.4 2.6 2.8 38221 f08 3.0 2.1 2.0 2.3 2.5 2.7 2.9 v ref maximum sense voltage minimum on-time considerations minimum on-time, t on(min) , is the smallest amount of time that the ltc3822-1 is capable of turning the top mosfet on. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. low duty cycle and high frequency applications may ap- proach the minimum on-time limit and care should be taken to ensure that: t v fv on min out osc in () ? <
ltc3822-1 18 38221f applications information if the duty cycle falls below what can be accommodated by the minimum on-time, the ltc3822-1 will begin to skip cycles. the output voltage will continue to be regulated, but the ripple current and ripple voltage will increase. the minimum on-time for the ltc3822-1 is typically about 170ns. however, as the peak sense voltage (i l(peak) ? r ds(on) ) decreases, the minimum on-time gradually increases up to about 260ns. ef? ciency considerations the ef? ciency of a switching regulator is equal to the output power divided by the input power. it is often useful to analyze individual losses to determine what is limiting ef? ciency and which change would produce the most improvement. ef? ciency can be expressed as: ef? ciency = 100% C (l1 + l2 + l3 + ) where l1, l2, etc. are the individual losses as a percent- age of input power. although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in ltc3822-1 circuits: 1) ltc3822-1 dc bias current, 2) mosfet gate charge current, 3) i 2 r losses and 4) transition losses. 1) the v in (pin) current is the dc supply current, given in the electrical characteristics, which excludes mosfet driver currents. v in current results in a small loss that increases with v in . 2) mosfet gate charge current results from switching the gate capacitance of the power mosfet. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from boost to ground. the resulting dq/dt is a current out of boost, which is typically much larger than the vin supply current. in continuous mode, i gatechg = f ? q p . 3) i 2 r losses are calculated from the dc resistances of the mosfets, inductor and/or sense resistor. in continuous mode, the average output current ? ows through l but is chopped between the top mosfet and the bottom mosfet. each mosfets r ds(on) can be multiplied by its respective duty cycle and summed together with the dcr of the inductor to obtain i 2 r losses. 4) transition losses apply to the external mosfet and increase with higher operating frequencies and input voltages. transition losses can be estimated from: transition loss = 2 ? v in 2 ? i o(max) ? c rss ? f other losses, including c in and c out esr dissipative losses and inductor core losses, generally account for less than 2% total additional loss. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to ( i load ) ? (esr), where esr is the effective se- ries resistance of c out . i load also begins to charge or discharge c out generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. opti-loop compensation allows the transient response to be optimized over a wide range of output capacitance and esr values. the i th series rc-cc ? lter (see the functional diagram) sets the dominant pole-zero loop compensation. the i th external components showed in the ? gure on the ? rst page of this data sheet will provide adequate compen- sation for most applications. the values can be modi? ed slightly (from 0.2 to 5 times their suggested values) to optimize transient response once the ? nal pc layout is done and the particular output capacitor type and value have been determined. the output capacitor needs to be decided upon because the various types and values determine the loop feedback factor gain and phase. an output current pulse of 20% to 100% of full load current having a rise time of 1s to 10s will produce output voltage and i th pin waveforms that will give a sense of the overall loop stability. the gain of the loop will be increased by increas- ing rc and the bandwidth of the loop will be increased by decreasing cc. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. for a detailed explanation of optimizing the compensation
ltc3822-1 19 38221f applications information components, including a review of control loop theory, refer to application note 76. a second, more severe transient is caused by switching in loads with large (>1f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. the only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25) ? (c load ). thus a 10f capacitor would be require a 250s rise time, limiting the charging current to about 200ma. design example for a design example, v in will be a 3.3v power supply. output voltage is 1.8v with a load current requirement of 8a. the iprg pin will be tied to v in and plllpf will be left ? oating, so the maximum current sense threshold v sense(max) will be approximately 200mv and the switch- ing frequency will be 550khz. duty cycle v v out in .% == 54 5 from figure 1, sf = 88%. rsf v i ds on max sense max out max () () () ?.? ? ? = 5 6 09 ? ? t = 0 013 . ? the si4466dy has an r ds(on) of 0.013 . to prevent inductor saturation during a short circuit, the inductor current rating should be higher than 16a. for 3.2a i ripple , the required minimum inductor value is: l v khz a v v h min = ? ? ? ? ? ? = 18 550 4 1 18 33 047 . ? ?C . . . a vishay ihlp2525cz-01 (0.47h, 17.5a) inductor works well for this application. c in will require an rms current rating of at least 5a at temperature. a low esr ceramic c out will allow ap- proximately 15mv output ripple. figure 10 shows an 8a, 3.3v in /1.8v out application. pc board layout checklist when laying out the printed circuit board, use the following checklist to ensure proper operation of the ltc3822-1. figure 9 shows a suggested pcb ? oorplan. ? the power loop (input capacitor, mosfet, inductor, output capacitor) and high di/dt loop (v in , through both mosfets to power gnd and back through c in to v in ) should be as small as possible and located on one layer. excess inductance here can cause increased stress on the mosfets and increased high frequency ringing on the output. ? put the feedback resistors close to the v fb pins. the i th compensation components should also be very close to the ltc3822-1. all small-signal circuitry should be isolated from the main switching loop with ground kelvin connected to the output capacitor ground. ? the current sense traces (v in and sw) should be kelvin connected right at the topside mosfet source and drain. the positive current sense pin is shared with the v in pin. this must not be locally decoupled with a capacitor. ? keep the switch node (sw) and the gate driver nodes (tg, bg) away from the small-signal components, es- pecially the feedback resistors, and i th compensation components. ? place c b as close as possible to the sw and boost pins. this capacitor carries high di/dt mosfet gate drive currents. the charging current to the boost diode should be provided from a separate v in trace than that to the v in pin. ? beware of ground loops in multiple layer pc boards. try to maintain one central signal ground node on the board. if the ground plane must be used for high dc currents, keep that path away from small-signal components.
ltc3822-1 20 38221f figure 10. 3.3v in 1.8v/8a high ef? ciency 550khz step-down converter applications information v out v in gnd gnd sw and other small-signal components gnd sense trace m1 m2 u1 l1 c out c in 38221 f09 figure 9. ltc3822-1 suggested pcb floorplan 22 f 2 v in 2.75v to 4.5v v out 1.8v 8a 38221 f10 10.2k 1000pf iprg v in plllpf sw boost tg run sync/mode i th v fb bg gnd *tdk c3216x5r0jl176m ltc3822edd-1 track/ss 59k 1% 0.22 f ihlp-2525cz-01 0.47 h 47 f* 2 fds6898a d optional 27pf 118k 1% 27pf
ltc3822-1 21 38221f figure 11. 3.3v in 1.8v/12a high ef? ciency high current 300khz step-down converter applications information 47 f 2 si7882dp *taiyo yuden jmk325bj107mm **toko fdu0650 si7882dp v in 3.3v v out 1.8v 12a 38221 f07 13.7k 1m 680pf iprg v in plllpf sw sense C boost tg run pgood sync/mode i th v fb bg gnd ltc3822egn-1 track/ss 59k 1% 0.22 f 0.56 h** 100 f* 2 33pf 118k 1% 68pf load current (ma) 65 efficiency (%) 95 60 55 90 75 85 80 70 10 1000 10000 100000 38221 f11b 50 100 burst mode operation pulse skipping continuous mode v out 200mv/div ac coupled inductor current 5a/div v in = 3.3v v out = 1.8v forced continuous mode 1a to 6a 50 s/div 38221 f11c ef? ciency load step
ltc3822-1 22 38221f applications information 22 f 2 v in 3.3v v out 1.1v 8a 38221 f12a 64.9k 470pf iprg v in plllpf sw boost tg run sync/mode i th v fb bg gnd *sanyo 2r5tpe220m9 **toko fdv0630 ltc3822edd-1 track/ss external oscillator 700khz 59k 1% 0.20 f 0.20 h** 10 f x5r si7940dp si7940dp 220 f* 10nf 33pf 10k 49.9k 1% 82pf figure 12. externally synchronized 700khz, 3.3v in , 1.1v/8a step-down converter load current (ma) 10 40 efficiency (%) 50 60 70 80 100 1000 10000 38221 f12b 30 20 10 0 90 v out 50mv/div ac coupled inductor current 2a/div v in = 3.3v v out = 1.1v load step 300ma to 3.3a 50 s/div 38221 f12c ef? ciency load step
ltc3822-1 23 38221f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. dd package 12-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1725 rev a) package description gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) 3.00 0.10 (4 sides) note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad and tie bars shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom viewexposed pad 1.65 0.10 0.75 0.05 r = 0.115 typ 1 6 12 7 pin 1 top mark (see note 6) 0.200 ref 0.00 C 0.05 (dd12) dfn 0106 rev a 0.23 0.05 pin 1 notch r = 0.20 or 0.25 45 chamfer 2.38 0.10 2.25 ref 0.45 bsc recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.25 0.05 2.25 ref 2.38 0.05 1.65 0.05 2.10 0.05 0.70 0.05 3.50 0.05 package outline 0.45 bsc gn16 (ssop) 0204 12 3 4 5 6 7 8 .229 C .244 (5.817 C 6.198) .150 C .157** (3.810 C 3.988) 16 15 14 13 .189 C .196* (4.801 C 4.978) 12 11 10 9 .016 C .050 (0.406 C 1.270) .015 .004 (0.38 0.10) 45 0 C 8 typ .007 C .0098 (0.178 C 0.249) .0532 C .0688 (1.35 C 1.75) .008 C .012 (0.203 C 0.305) typ .004 C .0098 (0.102 C 0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 C .165 .0250 bsc .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale
ltc3822-1 24 38221f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2006 lt 1006 ? printed in usa related parts part number description comments ltc1628/ltc3728 dual high ef? ciency, 2-phase synchronous step down controllers constant frequency, standby, 5v and 3.3v ldos, v in to 36v, 28-lead ssop ltc1735 high ef? ciency synchronous step-down controller burst mode operation, 16-pin narrow ssop, fault protection, 3.5v v in 36v ltc1778 no r sense , synchronous step-down controller current mode operation without sense resistor, fast transient response, 4v v in 36v ltc3411 1.25a (i out ), 4mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.5v to 5.5v, v out 0.8v, i q = 60a, i sd = <1a, ms package ltc3412 2.5a (i out ), 4mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.5v to 5.5v, v out 0.8v, i q = 60a, i sd = <1a, tssop-16e package ltc3416 4a, 4mhz, monolithic synchronous step-down regulator tracking input to provide easy supply sequencing, 2.25v v in 5.5v, 20-lead tssop package ltc3418 8a, 4mhz, synchronous step-down regulator tracking input to provide easy supply sequencing, 2.25v v in 5.5v, qfn package ltc3708 2-phase, no r sense , dual synchronous controller with output tracking constant on-time dual controller, v in up to 36v, very low duty cycle operation, 5mm 5mm qfn package ltc3736/ltc3736-2 2-phase, no r sense , dual synchronous controller with output tracking 2.75v v in 9.8v, 0.6v v out v in , 4mm 4mm qfn ltc3736-1 low emi 2-phase, dual synchronous controller with output tracking integrated spread spectrum for 20db lower noise, 2.75v v in 9.8v ltc3737 2-phase, no r sense , dual dc/dc controller with output tracking 2.75v v in 9.8v, 0.6v v out v in , 4mm 4mm qfn ltc3772/ltc3772b micropower no r sense step-down dc/dc controller 2.75v v in 9.8v, 3mm 2mm dfn or 8-lead sot-23, ltc3776 dual, 2-phase, no r sense synchronous controller for ddr/ qdr memory termination provides v ddq and v tt with one ic, 2.75v v in 9.8v, adjustable constant frequency with pll up to 850khz, spread spectrum operation, 4mm 4mm qfn and 24-lead ssop packages ltc3808 low emi, synchronous controller with output tracking 2.75v v in 9.8v, 4mm 3mm dfn, spread spectrum for 20db lower peak noise ltc3809/ltc3809-1 no r sense synchronous controller with output tracking 2.75v v in 9.8v, 3mm 3mm dfn and 10-lead msope packages ltc3822 no r sense low input voltage, all n-channel mosfet, synchronous step-down dc/dc controller 2.75v v in 4.5v, 0.6v v out v in , 10-lead ms and 3mm 3mm dfn packages ltc3830 high power synchronous step-down controller for low voltages (3v to 8v) 3v v in 8v, 500khz, s8, s16 and ssop-16 packages ltc3836 dual no r sense low input voltage, all n-channel mosfet, synchronous step-down dc/dc controller 2.75v v in 4.5v, 0.6v v out v in , 4mm 5mm qfn and 28-lead ssop packages

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